Using a shuffle unit to implement shift operations in a processor

Abstract

A method and mechanism for performing shift operations using a shuffle unit. A processor includes a shuffle unit configured to perform shuffle operations responsive to shuffle instructions. The shuffle unit is adapted to support shift operations as well. In response to determining a shuffle instruction is received, selected bits of an immediate value of the shuffle instruction are used to generate byte selects for relocating bytes of a source operand. In response to determining the instruction is a shift instruction, the shuffle unit performs an arithmetic operation on a first and second value, where the first value corresponds to a particular destination byte position, and the second value corresponds to the immediate value. The result of the arithmetic operation comprises a byte select which selects one of the bytes of a source operand for conveyance to the particular destination byte position. In the event a destination byte position should be cleared by the shift operation, the output for the particular destination byte position is forced to zero.