The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2008
Filed:
Feb. 03, 2005
Brian David Barrick, Pflugerville, TX (US);
Dwain Alan Hicks, Pflugerville, TX (US);
Takeki Osanai, Austin, TX (US);
David Scott Ray, Georgetown, TX (US);
Brian David Barrick, Pflugerville, TX (US);
Dwain Alan Hicks, Pflugerville, TX (US);
Takeki Osanai, Austin, TX (US);
David Scott Ray, Georgetown, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.