The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2008

Filed:

Aug. 08, 2003
Applicants:

Tsuyoshi Muramatsu, Nara, JP;

Hidekazu Yamanaka, Tenri, JP;

Atsushi Tokura, Tenri, JP;

Takuji Urata, Yamatokooriyama, JP;

Inventors:

Tsuyoshi Muramatsu, Nara, JP;

Hidekazu Yamanaka, Tenri, JP;

Atsushi Tokura, Tenri, JP;

Takuji Urata, Yamatokooriyama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A self-synchronous FIFO memory device () has a structure in which n self-synchronous data transmission lines (-) are arrayed in parallel. An input control section () selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a preceding-stage section. Further, an output control section () selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a succeeding-stage section.


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