The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2008
Filed:
May. 24, 2002
Subhash C. Roy, Lexington, MA (US);
David K. Toebes, Andover, MA (US);
Michael M. Renault, Medway, MA (US);
Steven E. Benoit, Walpole, MA (US);
Igor Zhovnirovsky, Newton Center, MA (US);
Subhash C. Roy, Lexington, MA (US);
David K. Toebes, Andover, MA (US);
Michael M. Renault, Medway, MA (US);
Steven E. Benoit, Walpole, MA (US);
Igor Zhovnirovsky, Newton Center, MA (US);
Other;
Abstract
Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.