The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2008
Filed:
Oct. 04, 2006
Cheng-yen Huang, Hsin-Chu, TW;
Cheng-Yen Huang, Hsin-Chu, TW;
Faraday Technology Corp., Hsin-Chu, TW;
Abstract
A de-skew multiplier clock synthesizer with a clock divider outside the feedback loop of a PLL is provided. The clock synthesizer includes a phase locked loop (PLL), a clock divider, and a phase comparator. The PLL receives a reference clock and generates a PLL output clock. The clock divider receives the PLL output clock and generates a first output clock. The phase comparator receives the reference clock, the PLL output clock, and the first output clock and generates a phase difference signal. The clock divider adjusts the first output clock to be in phase with the reference clock according to the phase difference signal.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile