The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2008

Filed:

Oct. 26, 2006
Applicants:

Hidetoshi Muramoto, Okazaki, JP;

Akira Yamada, Nukata-gun, JP;

Tomohisa Suzuki, Okazaki, JP;

Inventors:

Hidetoshi Muramoto, Okazaki, JP;

Akira Yamada, Nukata-gun, JP;

Tomohisa Suzuki, Okazaki, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes: a SOI substrate having a SOI layer, a buried oxide layer and a support substrate; multiple first separation trenches on the SOI layer; multiple MOS transistors, each of which is surrounded with one first separation trench; a second separation trench on the SOI layer including n-ply field trenches; and multiple field regions such that a k-th field region is surrounded with a k-th field trench. One MOS transistor is disposed in each field region. The MOS transistors are connected in series. The first MOS transistor has a gate terminal as an input terminal. The n-th MOS transistor is connected to the power source potential through an output resistor. The n-th field region has an electric potential, which is fixed to the power source potential.


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