The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2008

Filed:

Aug. 16, 2005
Applicants:

Igor Peidous, Fishkill, NY (US);

Martin Gerhardt, Dresden, DE;

David E. Brown, Pleasant Valley, NY (US);

Inventors:

Igor Peidous, Fishkill, NY (US);

Martin Gerhardt, Dresden, DE;

David E. Brown, Pleasant Valley, NY (US);

Assignee:

Advanced Micro Devices, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods are provided for fabricating a stressed MOS device. One method comprises the steps of providing a substrate of a monocrystalline semiconductor material having a first lattice constant, and forming a conductive gate electrode overlying the substrate, the gate electrode having opposing sides and having a thickness. Sidewall spacers are formed on the opposing sides of the gate electrode and trenches are etched in the semiconductor substrate in alignment with the sidewall spacers. A portion of the thickness of the conductive gate electrode is also etched to leave a remaining portion of the conductive gate electrode. A stress inducing layer of material is grown on the remaining portion of the conductive gate electrode and filling the trenches, the stress inducing layer of material having a second lattice constant different than the first lattice constant.


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