The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Jul. 21, 2006
Yi-lin Tsai, Kaohsiung, TW;
Tei-wei Kuo, Taipei, TW;
Jen-wei Hsieh, Taipei, TW;
Yuan-hao Chang, Tainan, TW;
Hsiang-chi Hsieh, Taipei, TW;
Yi-Lin Tsai, Kaohsiung, TW;
Tei-Wei Kuo, Taipei, TW;
Jen-Wei Hsieh, Taipei, TW;
Yuan-Hao Chang, Tainan, TW;
Hsiang-Chi Hsieh, Taipei, TW;
Genesys Logic, Inc., Taipei, TW;
Abstract
A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block. By forming correspondence among the physical erase unit, segment, frame, page, virtual erase unit, area, memory logical block and cluster to control the data access to the flash memory, the present invention achieves the reconfiguration and management of memory consumption and access efficiency for the flash memory.