The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Feb. 11, 2005
Son Dao Trong, Stuttgart, DE;
Juergen Haess, Schoenaich, DE;
Christian Jacobi, Boeblingen, DE;
Klaus Michael Kroener, Boeblingen, DE;
Silvia Melitta Mueller, Altdorf, DE;
Jochen Preiss, Boeblingen, DE;
Son Dao Trong, Stuttgart, DE;
Juergen Haess, Schoenaich, DE;
Christian Jacobi, Boeblingen, DE;
Klaus Michael Kroener, Boeblingen, DE;
Silvia Melitta Mueller, Altdorf, DE;
Jochen Preiss, Boeblingen, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The invention proposes a Floating Point Unit () with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic () which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic () which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic () which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic () which adds the outputs of the alignment logic () and the multiply logic (), with a normalization logic () which normalizes the output of the adder logic (), which is characterized in that a leading zero logic () is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic () is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic () output have all the same value in order to: a) control the carry logic of the adder logic () and/or b) control a stage of the normalization logic ().