The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Jul. 07, 2004
Minoru Saeki, Tokyo, JP;
Daisuke Suzuki, Tokyo, JP;
Minoru Saeki, Tokyo, JP;
Daisuke Suzuki, Tokyo, JP;
Mitsubishi Electric Corporation, Tokyo, JP;
Abstract
It is a purpose to evaluate a tamper resistance of an actual circuit with a high accuracy and at a high speed in an upstream process of a circuit design. A tamper resistance evaluating apparatus includes a signal change time counter unitfor counting the number of times a signal in a logic circuit changes, a power consumption calculation unitfor calculating a power consumption in the logic circuit based on the number of times a signal changes, which is counted by the signal change time counter unit, a leaked-information analysis unitfor analyzing information leaked from the logic circuit based on the power consumption in the logic circuit calculated by the power consumption calculation unit, a file databasefor storing a file used by a simulator, a simulation control information producing unitfor producing control information for controlling the logic simulator, a time sequence electric power information producing unitfor producing time sequence electric power information, in which the power consumptions calculated by the power consumption calculation unitare arranged in a time sequence, and a result displaying unitfor displaying the time sequence electric power information.