The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Mar. 29, 2007
Applicant:
Hiroyuki Sadakata, Osaka, JP;
Inventor:
Hiroyuki Sadakata, Osaka, JP;
Assignee:
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Through setting an internal test mode, a refresh operation for a DRAM is carried out by externally inputted address signals, instead of internally generated address signals, while maintaining the same number of memory cell arrays to be activated as that of memory cell arrays which are concurrently activated in a refresh for memory cell arrays. This configuration needs no drastic addition of circuits and allows a reduction in disturb test time for a plurality of memory cell arrays.
Sadakata, Hiroyuki. (2008). Semiconductor memory device (U.S. Patent No. 7460426). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7460426
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