The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Sep. 26, 2006
Hiroshi Tsuchi, Tokyo, JP;
Masao Iriguchi, Tokyo, JP;
Hiroshi Tsuchi, Tokyo, JP;
Masao Iriguchi, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
Disclosed is a multi-level output differential amplifier which includes a first differential pair; a second differential pair; a load circuit commonly connected to output pairs of the first and second differential pairs; first and second current sources for supplying current to the first and second differential pairs, respectively; an amplifier stage for receiving a common output signal of the first and second differential pairs and driving an output terminal by a charging or discharging operation; and a control circuit for controlling changeover of signal inputs to the first and second differential pairs. The data output period includes first and second time periods. In the first time period, a voltage at the output terminal and a reference voltage are applied to first and second differential inputs of the first differential pair; the output-terminal voltage and the reference voltage are stored in first and second capacitors, respectively, connected to the first and second differential inputs of the first differential pair; and first and second voltages are applied to first and second differential inputs of the second differential pair. In the second time period, the first and second differential inputs of the first differential pair are cut off from supply of the output-terminal voltage and supply of the reference voltage and are supplied with the voltages stored in the first and second capacitors, and the output-terminal voltage and a third voltage are applied to the first and second differential inputs of the second differential pair.