The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Mar. 31, 2006
Maximilian Fleischer, Höhenkirchen, DE;
Uwe Lampe, Buxtehude, DE;
Hans Meixner, Haar, DE;
Roland Pohle, Herdweg, DE;
Ralf Schneider, München, DE;
Elfriede Simon, München, DE;
Maximilian Fleischer, Höhenkirchen, DE;
Uwe Lampe, Buxtehude, DE;
Hans Meixner, Haar, DE;
Roland Pohle, Herdweg, DE;
Ralf Schneider, München, DE;
Elfriede Simon, München, DE;
Micronas GmbH, Freiburg, DE;
Abstract
A gas-sensitive field-effect transistor may be formed from a substrate with a gas-sensitive layer and a transistor processed separately and then assembled. The substrate may be patterned to form spacers by which the height of an air gap between the transistor and the sensitive layer may be adjustable to a relatively precise degree. Formation of the spacers can be achieved by patterning the substrate using material-removal techniques. The height of the spacers may be adjusted in the layer thickness of the gas-sensitive layer and for the transistor fabricated using a CMOS process. Suitable techniques for producing recesses between the spacers include, for example, polishing, cutting, sandblasting, lithographic dry etching, or wet-chemical etching. Suitable materials for the substrate may include, for example, glass, ceramic, aluminum oxide, silicon, or a dimensionally stable polymer. Following preparation of the substrate and the transistor, the two elements of the transistor are joined, for example, using flip-chip methods or adhesive-bonding technology.