The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Apr. 26, 2006
Carlos A. Paz DE Araujo, Colorado Springs, CO (US);
Larry D. Mcmillan, Colorado Springs, CO (US);
Narayan Solayappan, Colorado Springs, CO (US);
Vikram Joshi, Colorado Springs, CO (US);
Carlos A. Paz de Araujo, Colorado Springs, CO (US);
Larry D. McMillan, Colorado Springs, CO (US);
Narayan Solayappan, Colorado Springs, CO (US);
Vikram Joshi, Colorado Springs, CO (US);
Symetrix Corporation, Colorado Springs, CO (US);
Abstract
A three-dimensional ('3-D') memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm, and the corresponding capacitance area is typically in a range of from 0.4 nmto 1.0 nmThe ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.