The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2008
Filed:
Oct. 30, 2006
David Baker, Chapel Hill, NC (US);
Christopher Basoglu, Bothell, WA (US);
Benjamin Cutler, Seattle, WA (US);
Richard Deeley, San Jose, CA (US);
Gregorio Gervasio, Sunnyvale, CA (US);
Atsuo Kawaguchi, San Jose, CA (US);
Keiji Kojima, Sagamihara, JP;
Woobin Lee, Lynnwood, WA (US);
Takeshi Miyazaki, Tokyo, JP;
Yatin Mundkur, Sunnyvale, CA (US);
Vinay Naik, Austin, TX (US);
Kiyokazu Nishioka, Odawara, JP;
Toru Nojiri, Tokyo, JP;
John O'donnell, Seattle, WA (US);
Sarang Padalkar, San Jose, CA (US);
David Baker, Chapel Hill, NC (US);
Christopher Basoglu, Bothell, WA (US);
Benjamin Cutler, Seattle, WA (US);
Richard Deeley, San Jose, CA (US);
Gregorio Gervasio, Sunnyvale, CA (US);
Atsuo Kawaguchi, San Jose, CA (US);
Keiji Kojima, Sagamihara, JP;
Woobin Lee, Lynnwood, WA (US);
Takeshi Miyazaki, Tokyo, JP;
Yatin Mundkur, Sunnyvale, CA (US);
Vinay Naik, Austin, TX (US);
Kiyokazu Nishioka, Odawara, JP;
Toru Nojiri, Tokyo, JP;
John O'Donnell, Seattle, WA (US);
Sarang Padalkar, San Jose, CA (US);
Hitachi, Ltd., , JP;
Abstract
An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.