The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2008
Filed:
Sep. 07, 2007
Arthur A. Bright, Croton-on-Hudson, NY (US);
Paul G. Crumley, Yorktown Heights, NY (US);
Marc Dombrowa, Bronx, NY (US);
Steven M. Douskey, Rochester, MN (US);
Rudolf A. Haring, Cortlandt Manor, NY (US);
Steven F. Oakland, Colchester, VT (US);
Michael R. Quellette, Westford, VT (US);
Scott A. Strissel, Byron, MN (US);
Arthur A. Bright, Croton-on-Hudson, NY (US);
Paul G. Crumley, Yorktown Heights, NY (US);
Marc Dombrowa, Bronx, NY (US);
Steven M. Douskey, Rochester, MN (US);
Rudolf A. Haring, Cortlandt Manor, NY (US);
Steven F. Oakland, Colchester, VT (US);
Michael R. Quellette, Westford, VT (US);
Scott A. Strissel, Byron, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.