Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted

Abstract

A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.