The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7456671 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 25, 2008

Filed:

Jan. 11, 2007
Applicants:

Charlie C. Hwang, Hopewell Junction, NY (US);

Phillip J. Restle, Katonah, NY (US);

Leon J. Sigal, Monsey, NY (US);

Inventors:

Charlie C. Hwang, Hopewell Junction, NY (US);

Phillip J. Restle, Katonah, NY (US);

Leon J. Sigal, Monsey, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be synthesized by software to achieve desired delay resolution and range. Constant capacitive load of internal node enhances the linearity of achieved delay by digital controls.


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Hwang, Charlie. (2008). Hierarchical scalable high resolution digital programmable delay circuit (U.S. Patent No. 7456671). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7456671

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