The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2008
Filed:
Jul. 13, 2006
Hitoshi Okamura, Gyeonggi-do, KR;
Hitoshi Okamura, Gyeonggi-do, KR;
Samsung Electronics, Co., Ltd., Gyeonggi-do, KR;
Abstract
An output buffer circuit includes: a differential circuit; and first and second load circuits coupled between the differential circuit and a high power supply voltage VDDH. Such a differential circuit includes first and second NMOS transistors having low-voltage gate dielectric layers susceptible to deterioration at operation above a maximum gate-body voltage VgbMAX (where VDDH>VgbMAX), respectively. Body electrodes & source electrodes are coupled to a common node. Gate electrodes are coupled to first and second differential input signals, respectively, such that voltages on drains of the first and second NMOS transistors represent results of a differential switching operation, respectively. More particularly, the drains of the first and second NMOS transistors are coupled to the first and second loads. The common node is coupled to a bias voltage such that Vgb of the first & second NMOS transistors is VgbMAX≧Vgb.