The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2008

Filed:

Dec. 06, 2005
Applicant:

Jin Choi, Gyeonggi-do, KR;

Inventor:

Jin Choi, Gyeonggi-do, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a layout of a semiconductor memory device capable of minimizing an occupation area of a dummy cell array and a method of controlling capacitance of a dummy cell to be same with that of the memory cell. The layout includes a dummy cell connected to one side of a sense amplifier, in which the dummy cell has a capacitance identical to a capacitance of the memory cell. The dummy cell is connected to one side of a sense amplifier connected to the memory cell and arranged in a column direction of the semiconductor substrate.


Find Patent Forward Citations

Choi, Jin. (2008). Layout of semiconductor memory device and method of controlling capacitance of dummy cell (U.S. Patent No. 7456457). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7456457

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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