The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2008

Filed:

Nov. 29, 2004
Applicants:

Koichi Tahira, Nagasaki, JP;

Hiroki Usui, Kanagawa, JP;

Hiroshi Hasegawa, Kanagawa, JP;

Makoto Aikawa, Kanagawa, JP;

Inventors:

Koichi Tahira, Nagasaki, JP;

Hiroki Usui, Kanagawa, JP;

Hiroshi Hasegawa, Kanagawa, JP;

Makoto Aikawa, Kanagawa, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal cell region, a dummy gate electrode formed to have a comb-shaped pattern is formed on a vacant region, a wiring for applying a predetermined voltage is connected respectively to at least a part of the dummy gate and the semiconductor substrate (source drain regions), and an electrostatic capacity between the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of the power source.


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