The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2008

Filed:

Nov. 30, 2004
Applicants:

Rodney Hill, Mansfield, TX (US);

Victor M. Torres, Irving, TX (US);

Richard W. Foote, Jr., Kennedale, TX (US);

Inventors:

Rodney Hill, Mansfield, TX (US);

Victor M. Torres, Irving, TX (US);

Richard W. Foote, Jr., Kennedale, TX (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method is disclosed for providing an etch procedure to facet the top corners of a via in a semiconductor device. A vertical anisotropic dry etch process is applied through an aperture in a resist mask to etch through a dielectric layer down to a bottom conductor layer. The resist mask is removed and an etch process is applied to etch away corner portions of the dielectric layer. The etch process forms a flat sidewall surface in the portions of the dielectric layer that form the via. The flat sidewall surface is disposed at an obtuse angle with respect to the top surface of the dielectric layer and at an obtuse angle with respect to a vertical sidewall of the via cavity. The flat sidewall surface and the absence of sharp corners facilitate a subsequent metal fill process.


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