The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2008

Filed:

Aug. 28, 2007
Applicants:

Ha Chu VU, San Jose, CA (US);

Seema Varma, Sunnyvale, CA (US);

Inventors:

Ha Chu Vu, San Jose, CA (US);

Seema Varma, Sunnyvale, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus can be arranged with a correlated double sampler circuit (CDS) for processing an output signal from an imaging device such as a charge-coupled device (CCD) image sensor. The CDS circuit includes an amplifier, a set of capacitors that are dynamically configured for sampling and holding operations, and a reduced number of capacitive digital-to-analog converter (CDAC) circuits, all arranged in a ping-pong architecture. The described ping-pong architecture is useful in digital imaging applications such as digital scanners, digital copiers, digital cameras, and digital camcorders, to name a few.


Find Patent Forward Citations

Vu, Ha. (2008). Correlated double sampling ping-pong architecture with reduced dac capacitors (U.S. Patent No. 7453389). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7453389

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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