The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2008

Filed:

Aug. 29, 2006
Applicants:

David William Boerstler, Round Rock, TX (US);

Eric John Lukes, Stewartville, MN (US);

Hiroki Kihara, Austin, TX (US);

James David Strom, Rochester, MN (US);

Inventors:

David William Boerstler, Round Rock, TX (US);

Eric John Lukes, Stewartville, MN (US);

Hiroki Kihara, Austin, TX (US);

James David Strom, Rochester, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03K 23/00 (2006.01); H03K 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.


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