The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2008

Filed:

Feb. 13, 2007
Applicants:

Vladislav Potanin, San Jose, CA (US);

Elena Potanina, San Jose, CA (US);

Inventors:

Vladislav Potanin, San Jose, CA (US);

Elena Potanina, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for providing precise current regulation and limitation for a power supply is provided. The method includes amplifying any difference between a load current signal and a current setting reference signal with a feedback loop amplifier to generate a feedback signal. A power output signal is generated based on the feedback signal. An output signal for the power supply is generated based on the power output signal. The load current signal and the current setting reference signal are generated based on the power output signal. An offset error signal is generated based on the load current signal and the current setting reference signal. A differential bias for the feedback loop amplifier is adjusted based on the offset error signal.


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