The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7452790 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 18, 2008

Filed:

Dec. 22, 2004
Applicants:

Hye-hyang Park, Suwon-si, KR;

Ki-yong Lee, Yongin-si, KR;

Inventors:

Hye-Hyang Park, Suwon-si, KR;

Ki-Yong Lee, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C30B 28/02 (2006.01); C30B 29/06 (2006.01); H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a method of fabricating a thin film transistor in which, in order to control the concentration of metal catalysts remaining on a polycrystalline silicon layer when an amorphous silicon layer formed on an insulating substrate is crystallized into the polycrystalline silicon layer by a super grain silicon (SGS) crystallization method, the substrate is annealed so that a very small amount of metal catalyst is adsorbed or diffused into a capping layer, and then a crystallization process is carried out, thereby minimizing the concentration of the metal catalysts remaining on the polycrystalline silicon layer, as well as forming a thick metal catalyst layer. The method includes preparing an insulating substrate; sequentially forming an amorphous silicon layer, a capping layer, and a metal catalyst layer on the substrate; first annealing the substrate to adsorb or diffuse metal catalysts into the capping layer; removing the metal catalyst layer; second annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer by means of the metal catalyst; and removing the capping layer. Thus, with the method of fabricating the thin film transistor of the present invention, it is possible to minimize the concentration of the metal catalysts remaining on the polycrystalline silicon layer, as well as to form a thick metal catalyst layer.


Find Patent Forward Citations

Park, Hye-Hyang. (2008). Method of fabricating thin film transistor (U.S. Patent No. 7452790). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7452790

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