Semiconductor memory device and transmission/reception system provided with the same

Abstract

In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.