The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2008
Filed:
Dec. 21, 2006
Seiji Yamahira, Kyoto, JP;
Toshiki Mori, Osaka, JP;
Seiji Yamahira, Kyoto, JP;
Toshiki Mori, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second invertersandof a CMOS type in which a gate of each MOS transistor is individually driven are provided and the first inverteris used as a level converting unit. A voltage level of a first control signal CSoutput from an output node noof the first inverteris forcibly dropped down by a voltage dropping circuit CONTso as to accelerate the operation of the second inverter. As a result, the inversion of the level of an output signal of the first inverteris accelerated. Further, the balance between current capabilities of the individual transistors is optimized and, in particular, the sizes of the transistors constituting the second inverterare reduced so as to suppress an increase in a circuit area.