Semiconductor gate circuit and delay circuit comprising series connected cmos transistors

Abstract

A gate circuit has a complementary transistor structure comprising transistors of different conductivity types connected in series respectively between two power source terminals and an output terminal, sharing a gate connected to an input terminal, the transistors of different conductivity types each comprising plural transistors, and the plural transistors being connected in series between each of the two power source terminal and the output terminal. The gate is provided to extend like a line, plural diffusion layers are provided along the direction of the line in which the gate extends, and a conduction channel of each of the plural transistors connected in series between the power source terminals and the output terminal is formed in the diffusion layers.