The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7447618 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 04, 2008

Filed:

May. 11, 2005
Applicant:

David N. Steffen, Irvine, CA (US);

Inventor:

David N. Steffen, Irvine, CA (US);

Assignee:

QLOGIC, Corporation, Aliso Viejo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method and system for testing an Application Specific Integrated Circuit is provided. The system includes, a simulator that interfaces with a host computer emulation module; and a virtual interface driver ('VID') that interfaces with the host computer emulation module and a bus interface module, wherein the VID maps plural stimulus to the simulator via the bus interface module. The method includes, loading a bus functional module in an ASIC simulator; determining configuration of devices supported by a host emulation system; and mapping configuration information to the host emulation system, wherein a virtual interface driver maps the configuration information to the host emulation system.


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Steffen, David. (2008). Method and system for asic simulation (U.S. Patent No. 7447618). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7447618

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