The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2008

Filed:

Jun. 01, 2005
Applicants:

Ke-chiang Huang, Hsinchu, TW;

Kuo-feng Hsu, Jhudong Township, Hsinchu County, TW;

Jiunn-yih Lee, Hsinchu, TW;

Hsian-feng Liu, Fongshan, TW;

Inventors:

Ke-Chiang Huang, Hsinchu, TW;

Kuo-Feng Hsu, Jhudong Township, Hsinchu County, TW;

Jiunn-Yih Lee, Hsinchu, TW;

Hsian-Feng Liu, Fongshan, TW;

Assignee:

Mstar Semiconductor, Inc., Hsinchu County, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes. The device comprises: a programmable equalizer, having a plurality of equalizing modes, receiving an original signal so as to output an equalized signal; a phase-locked loop, receiving a reference clock signal and a first control signal so as to output first sampling pulses and second sampling pulses; a data slicing device, coupled to the phase-locked loop and the programmable equalizer and receiving the first sampling pulses, the second sampling pulses and the equalized signal so as to output a first slicing signal and a second slicing signal; and a signal processing device, coupled to the data slicing device and receiving the first slicing signal and the second slicing signal so as to output the first control signal and a second control signal; wherein the signal processing device programs the programmable equalizer by using the second control signal so as to select an equalizing mode from the plurality of equalizing modes for the programmable equalizer.


Find Patent Forward Citations

Loading…