The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2008

Filed:

Dec. 18, 2003
Applicants:

Atsushi Yajima, Tokyo, JP;

Kazuhisa Funamoto, Tokyo, JP;

Yasunari Ikeda, Kanagawa, JP;

Inventors:

Atsushi Yajima, Tokyo, JP;

Kazuhisa Funamoto, Tokyo, JP;

Yasunari Ikeda, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 27/00 (2006.01); H04L 27/10 (2006.01); H03K 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

An OFDM receiver () is provided which includes a clock-frequency error calculation circuit () to calculate a difference in clock frequency between a clock for a received signal and an operation clock used in the receiver (), and a guard correlation/peak detection circuit () to determine an autocorrelation of a guard interval and detect a peak timing of the correlation signal. The guard correlation/peak detection circuit () incorporates a free-running counter, and outputs a count of the free-running counter at the peak timing to the clock-frequency error calculation circuit (). The clock-frequency error calculation circuit () uses a plurality of time-change rate detection circuits provided at different time intervals to calculate a time-change rate of an input count. The clock-frequency error calculation circuit () plots the time-change rates to generate a histogram and calculates a clock-frequency error from the histogram.


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