The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2008
Filed:
Mar. 27, 2006
System and method for providing a cmos compatible single poly eeprom with an nmos program transistor
Jiankang Bu, Windham, ME (US);
Lee Jacobson, Cape Elizabeth, ME (US);
David Courtney Parker, Topsham, ME (US);
Jiankang Bu, Windham, ME (US);
Lee Jacobson, Cape Elizabeth, ME (US);
David Courtney Parker, Topsham, ME (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A system and method is disclosed for providing a CMOS compatible single poly electrically erasable programmable read only memory (EEPROM) with memory cells that comprise an NMOS program transistor. In a first embodiment the memory cells of the EEPROM comprise a PMOS control capacitor. In a second embodiment the memory cells of the EEPROM comprise an NMOS control capacitor. A well bias voltage is applied to the NMOS program transistor instead of a gate bias voltage. The well bias voltage enables the injection of (1) channel hot electrons, (2) second hot electrons initiated by the channel hot electrons, and (3) drain impact ionization hot electrons into a floating gate of the NMOS program transistor.