Manufacturing process for lateral power mos transistors

Abstract

A process manufactures power MOS lateral transistors together with CMOS devices on a semiconductor substrate. The process forms a lateral MOS transistor having a gate electrode on the semiconductor region, a source comprising a first highly doped portion aligned with the gate electrode and a drain comprising a lightly doped portion aligned with the gate electrode and a second highly doped portion included in the lightly doped portion. The process forms on the lightly doped portion, a protective layer of a first material; forms on the lateral MOS transistor, a dielectric layer of a second material selectively etchable with respect to the first material; forms, in the dielectric layer first, second, and third openings; and fills the openings with a conductive layer that forms drain and source contacts electrically connected to the first and second highly doped portions, and one electrical shield substantially aligned with the protective layer.