The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2008

Filed:

Sep. 27, 2002
Applicant:

Steven R. Jahnke, Tokyo, JP;

Inventor:

Steven R. Jahnke, Tokyo, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
Abstract

In an embedded symmetric multiprocessor (ESMP) system it is desirable to maintain equal central processing unit load balance. When an interrupt occurs, a single central processing receives the interrupt and then passes information to the central processing unit scheduling software. This software will in turn determine which central processing unit can best handle the interrupt. Because the scheduling software is able to determine which central processing unit handles the interrupt process, it can maintain central processing unit load balancing resulting in better system performance.


Find Patent Forward Citations

Jahnke, Steven. (2008). Load balanced interrupt handling in an embedded symmetric multiprocessor system (U.S. Patent No. 7444639). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7444639

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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