The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2008
Filed:
Oct. 28, 2004
Applicants:
Thai M. Nguyen, San Jose, CA (US);
William Shen, San Jose, CA (US);
Cam LU, Milpitas, CA (US);
Inventors:
Assignee:
LSI Corporation, Milpitas, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 7/00 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract
A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme provides for the ability to separately shut off either the memory functional clock source or the memory test clock source, provides that less power is required during production testing, and provides that simulation time is reduced during design verification because the functional logic is not clocked.