Reduced-power memory with per-sector ground control

Abstract

A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector ground control to advantageously reduce power consumption. Selective power control of a plurality of sectors comprised in the reduced-power memory is responsive to a subset of address bits for accessing the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via a decrease in ground potential from a retention level to an access level. Time needed to vary the ground potential is optionally masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.