The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2008

Filed:

Dec. 16, 2003
Applicants:

Robertus Theodorus Fransiscus Van Schaijk, Leuven, BE;

Michiel Slotboom, Leuven, BE;

Inventors:
Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 29/788 (2006.01); H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semiconductor devices on a substrate (), each device having a floating gate (), comprising: first forming isolation zones () in the substrate (), thereafter forming a floating gate separator () on the isolation zones () at locations where separations between adjacent floating gates () are to be formed, after forming the floating gate separator (), forming the floating gates () on the substrate () between parts of the floating gate separator (), and thereafter removing the floating gate separator () so as to obtain slits in between neighboring floating gates (). This method has an advantage over prior art in that less residues of floating gate material, or less floating gate material shorts between adjacent floating gates occur. Furthermore, the gate profile is damaged less than in prior art slit processing methods.


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