The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2008
Filed:
Dec. 02, 2005
Stephen W. Bedell, Wappingers Falls, NY (US);
Anthony G. Domenicucci, New Paltz, NY (US);
Keith E. Fogel, Mohegan Lake, NY (US);
Effendi Leobandung, Wappingers Falls, NY (US);
Devendra K. Sadana, Pleasantville, NY (US);
Stephen W. Bedell, Wappingers Falls, NY (US);
Anthony G. Domenicucci, New Paltz, NY (US);
Keith E. Fogel, Mohegan Lake, NY (US);
Effendi Leobandung, Wappingers Falls, NY (US);
Devendra K. Sadana, Pleasantville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.