The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2008
Filed:
Sep. 09, 2005
Method of manufacturing a transistor and a method of forming a memory device with isolation trenches
Peng-fei Wang, Dresden, DE;
Joachim Nuetzel, Dresden, DE;
Rolf Weis, Dresden, DE;
Till Schloesser, Dresden, DE;
Marc Strasser, Munich, DE;
Richard Johannes Luyken, Munich, DE;
Peng-Fei Wang, Dresden, DE;
Joachim Nuetzel, Dresden, DE;
Rolf Weis, Dresden, DE;
Till Schloesser, Dresden, DE;
Marc Strasser, Munich, DE;
Richard Johannes Luyken, Munich, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.