The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7440991 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 21, 2008

Filed:

Mar. 14, 2005
Applicants:

Tsuneki Sasaki, Kanagawa, JP;

Junichiro Minamitani, Kanagawa, JP;

Inventors:

Tsuneki Sasaki, Kanagawa, JP;

Junichiro Minamitani, Kanagawa, JP;

Assignee:

NEC Electronics Corporation, Kawasaki, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/508 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a digital circuit which comprises input signals A[n−1:0], SH[logn−1:0], and DAT[n−1:0], a barrel shifter for outputting data B[n−1:0] obtained by shifting the signal DAT by the bits of the signal SH, a group G·P·SUM computation stage for dividing each of the digits of the input signals A and B into groups of m bits, and computing Gs, Ps, and addition results SUMwhen carry inputs are high and addition results SUMwhen the carry inputs are low, a carry computation circuit for computing a carry for each of the groups, and a SUM selection stage for selecting a SUMor a SUMcomputed for each of the groups according to each carry output by the carry computation circuit.


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Sasaki, Tsuneki. (2008). Digital circuit (U.S. Patent No. 7440991). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7440991

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