The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2008

Filed:

Jul. 13, 2006
Applicants:

Ramnath Venkatraman, San Jose, CA (US);

Ruggero Castagnetti, Menlo Park, CA (US);

Subramanian Ramesh, Cupertino, CA (US);

Inventors:

Ramnath Venkatraman, San Jose, CA (US);

Ruggero Castagnetti, Menlo Park, CA (US);

Subramanian Ramesh, Cupertino, CA (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.


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