The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2008
Filed:
Feb. 21, 2007
Michael Rather, San Francisco, CA (US);
James G. Schleicher, Ii, Los Gatos, CA (US);
Michael Rather, San Francisco, CA (US);
James G. Schleicher, II, Los Gatos, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
The present invention is directed to a programmable logic device and a method of programming a programmable logic device that features providing a verification technique to ensure the requisite functional operations of an array of configurable logic blocks may be programmed while limiting a user from altering the functional operations of the configurable logic blocks of the programmable logic device to having functional operations in addition to and/or different from the functional operations of that a vendor desires a user to have. In this manner, the array of configurable logic blocks can be designed so that the same may be programmed to provide one or more of multiple different functional operations, while limiting a user to a desired set of functional operations.