The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2008

Filed:

May. 26, 2005
Applicants:

Yasunori Inoue, Gifu, JP;

Ryosuke Usul, Aichi, JP;

Yasuhiro Kohara, Gifu, JP;

Nobuhisa Takakusaki, Gunma, JP;

Takeshi Nakamura, Gunma, JP;

Inventors:

Yasunori Inoue, Gifu, JP;

Ryosuke Usul, Aichi, JP;

Yasuhiro Kohara, Gifu, JP;

Nobuhisa Takakusaki, Gunma, JP;

Takeshi Nakamura, Gunma, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/053 (2006.01); H01L 23/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a manufacturing method of a hybrid integrated circuit deviceaccording to the present invention, a first dummy pattern Dis provided on a first wiring layerA. Furthermore, a second dummy pattern Dis provided on a second wiring layerB. The first dummy pattern Dand the second dummy pattern Dare connected through a connection partwhich penetrates an insulation layer. Hence, heat dissipation through a dummy pattern can be actively performed. In addition, even in the cases where a multi-layered wiring is formed, it is possible to provide a circuit device which can secure a heat dissipation property.


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