The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2008
Filed:
Sep. 22, 2006
Hiroyuki Imamura, Osaka, JP;
Nobuyuki Koutani, Osaka, JP;
Yoshifumi Nakamura, Osaka, JP;
Kenshi Tokushima, Osaka, JP;
Hiroyuki Imamura, Osaka, JP;
Nobuyuki Koutani, Osaka, JP;
Yoshifumi Nakamura, Osaka, JP;
Kenshi Tokushima, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A circuit board including a flexible insulating substrate, a plurality of conductive wirings placed in line on the flexible insulating substrate, and bumps provided at end portions of the respective conductive wirings positioned in a region for mounting a semiconductor chip is provided. The circuit board further includes an auxiliary conductive wiring positioned at an outermost corner of the region for mounting the semiconductor chip, being adjacent to and an outside the outermost conductive wiring, and an auxiliary bump formed on the auxiliary conductive wiring in line with the bumps on the conductive wirings. One end portion of the auxiliary conductive wiring is terminated at a position in the outside vicinity of the auxiliary bump in an outward direction of the region for mounting the semiconductor chip, and the auxiliary conductive wiring is bent at the other end portion positioned inside the auxiliary bump in an inward direction of the region for mounting the semiconductor chip, and connected to an end of the adjacent outermost conductive wiring. A break in the outermost conductive wiring, which is caused by concentrated stress at the time of joining the bumps of the circuit board and electrode pads of the semiconductor chip, can be suppressed.