The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7439584 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 21, 2008

Filed:

Feb. 28, 2006
Applicants:

Vishnu K. Khemka, Phoenix, AZ (US);

Amitava Bose, Tempe, AZ (US);

Todd C. Roggenbauer, Chandler, AZ (US);

Ronghua Zhu, Chandler, AZ (US);

Inventors:

Vishnu K. Khemka, Phoenix, AZ (US);

Amitava Bose, Tempe, AZ (US);

Todd C. Roggenbauer, Chandler, AZ (US);

Ronghua Zhu, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices. A semiconductor device comprises a semiconductor substrate () of a first type; first and second terminals () laterally spaced-apart on a surface () above the substrate; a first semiconductor region () of the first type overlying the substrate and ohmically coupled to the first terminal (); a second semiconductor region () of a second opposite type in proximity to the first region and ohmically coupled to the first terminal; a third semiconductor region () of the second type overlying the substrate and ohmically coupled to the second terminal () and laterally arranged with respect to the first region; a parasitic vertical device comprising the first region and the substrate, the parasitic vertical device for permitting leakage current to flow from the first terminal to the substrate; a fourth semiconductor region () of the first type in proximity to the third region and ohmically coupled to the second terminal, thereby forming in combination with the third region a shorted base-collector region of a lateral transistor extending between the first and second terminals to provide diode action; a channel region () of the first type separating the first and third regions at the surface; a gate insulator () overlying the channel region; and a gate electrode () overlying the gate insulator.


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