Contactless nonvolatile memory array

Abstract

An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide stripe that runs under a portion of each, for example a portion running in the X-direction while the two Y-direction portions serve to establish a channel. Shared source/drain regions are established between and in proximity to the Y-direction portions to define two non-volatile memory transistors in each memory cell. Memory cells are replicated in the word line direction and then mirrored with respect to the word line to form the next row or column. This geometry is contactless because the word line and source/drain regions are all linear throughout the array so that electrical contact can be established outside of the array of cells. Each transistor can be addressed and thus programmed and erased or pairs of transistors in a line can be erased, i.e., sector erase.