The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2008
Filed:
Dec. 30, 2005
Shunpu LI, Cambridge, GB;
Christopher Newsome, Cambridge, GB;
David Russell, Cambridge, GB;
Thomas Kugler, Cambridge, GB;
Shunpu Li, Cambridge, GB;
Christopher Newsome, Cambridge, GB;
David Russell, Cambridge, GB;
Thomas Kugler, Cambridge, GB;
Seiko Epson Corporation, Tokyo, JP;
Abstract
Provided is a patterning method capable of fabricating high resolution structures without using a high resolution patterning step. The method comprises the steps of: (i) pre-patterning a layer of material () on a substrate (), (ii) spin-coating a solution of a film-forming substance over the pre-patterned substrate, (iii) drying the spin-coated solution to form a film () of the film-forming substance on the unpatterned areas of the substrate and on the surface and sides of the pre-patterned material, (iv) etching the dried film in such a way that it remains only around the sides of the pre-patterned material, and (v) removing the pre-patterned material to leave ridges () of the film-forming substance on the substrate, the pattern of the ridges corresponding to the outline of the pre-patterned material. A metal layer may then be deposited on the resulting patterned substrate followed by removal of the ridges leaving discrete areas of metal which form latent source and drain electrodes of a thin film transistor. An array of thin film transistors may then be formed by selectively depositing areas of semiconductor, insulator and conductor, the latter forming a gate electrode associated with each pair of source and drain electrodes.