The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2008
Filed:
Nov. 16, 2005
Albert Ren-rui Wang, Fremont, CA (US);
Richard Ruddell, Los Gatos, CA (US);
David William Goodwin, Sunnyvale, CA (US);
Earl A. Killian, Los Altos Hills, CA (US);
Nupur Bhattacharyya, Mountain View, CA (US);
Marines Puig Medina, San Jose, CA (US);
Walter David Lichtenstein, Belmont, MA (US);
Pavlos Konas, Mountain View, CA (US);
Rangarajan Srinivasan, Los Gatos, CA (US);
Christopher Mark Songer, Mountain View, CA (US);
Akilesh Parameswar, San Jose, CA (US);
Dror E. Maydan, Palo Alto, CA (US);
Ricardo E. Gonzalez, Menlo Park, CA (US);
Albert Ren-Rui Wang, Fremont, CA (US);
Richard Ruddell, Los Gatos, CA (US);
David William Goodwin, Sunnyvale, CA (US);
Earl A. Killian, Los Altos Hills, CA (US);
Nupur Bhattacharyya, Mountain View, CA (US);
Marines Puig Medina, San Jose, CA (US);
Walter David Lichtenstein, Belmont, MA (US);
Pavlos Konas, Mountain View, CA (US);
Rangarajan Srinivasan, Los Gatos, CA (US);
Christopher Mark Songer, Mountain View, CA (US);
Akilesh Parameswar, San Jose, CA (US);
Dror E. Maydan, Palo Alto, CA (US);
Ricardo E. Gonzalez, Menlo Park, CA (US);
Tensilica, Inc., Santa Clara, CA (US);
Abstract
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.