The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2008

Filed:

Feb. 20, 2004
Applicants:

Leon Zheng, San Jose, CA (US);

Martin Langhammer, Alderbury, GB;

Steven Perry, High Wycombe, GB;

Paul Metzgen, Chiswick, GB;

Gregory Starr, San Jose, CA (US);

William Hwang, Fremont, CA (US);

Kumara Tharmalingam, Santa Clara, CA (US);

Inventors:

Leon Zheng, San Jose, CA (US);

Martin Langhammer, Alderbury, GB;

Steven Perry, High Wycombe, GB;

Paul Metzgen, Chiswick, GB;

Gregory Starr, San Jose, CA (US);

William Hwang, Fremont, CA (US);

Kumara Tharmalingam, Santa Clara, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.


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